(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to field effect transistors having deep sub-micron channel lengths with reduced gate-to-drain capacitance and improved short channel effects.
(2) Description of the Prior Art
Advances in the semiconductor process technologies in the past few years have dramatically decreased the device feature sizes and increased the circuit density and performance on integrated circuit chips. The device most used for Ultra Large Scale Integration (ULSI) is the Field Effect Transistor (FET), having a silicon gate electrode with self-aligned source/drain contact areas. The popular choice of FETs is because of their very small size, high packing density, low power consumption, and high yields.
The conventional FETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single-crystal semiconductor substrate. The gate electrode structure is used as a diffusion or implant barrier mask to form self-aligned source/drain areas in the substrate adjacent to the sides of the gate electrode. The distance from the source junction to drain. junction under the gate electrode is defined as the channel length of the FET.
Advances in semiconductor technologies, such as high-resolution photolithographic techniques and anisotropic plasma etching, to name a few, have reduced the minimum feature sizes of devices to much less than a micrometer (um or 1.0.times.10.sup.-4 centimeters, commonly referred to as a micron). For example, in the industry FETs are currently used having channel lengths that are less than a half-micrometer (about 0.35 um) in length. If further increases in circuit density and device performance are to continue, then device minimum feature sizes, and more specifically the FET channel length, must be reduced to deep sub-micron dimensions (that is, to less than 0.20 um).
However, as this downscaling continues and the channel length is further reduced in length, the FET device experiences a number of undesirable electrical characteristics known as short channel effects (SCE). These short channel effects become more severe as the device physical dimensions and, more specifically, as the FET channel length is scaled down. This result is due to the fact that the band gap and built-in potential at junctions are an intrinsic property (constant) of the crystalline materials (such as silicon), and are non-scalable with the further reduction in device dimensions.
These adverse short channel effects result from the electric field distribution in the channel area when the integrated circuit is powered up, which lead to a number of problems. For example, electrons ejected from the drain can acquire sufficient energy to be injected into the gate oxide resulting in charge buildup in the oxide that causes threshold voltage shifts. Unfortunately, this hot carrier effect (HCE) can degrade device performance after the product is in use (at the customer).
One method of minimizing these short channel effects, common practice in the semiconductor industry, is to fabricate FET structures with Lightly Doped Drains (LDDs). These LDD FET structures have low dopant concentration in the drain regions adjacent to the gate electrodes, and modify the electric fields in the drains so as to minimize or eliminate short channel effects, such as hot carrier effects.
Typically, the LDD FETs are formed by using two ion implantations. After forming the polysilicon gate electrodes, a first implant, using the gate electrodes as an implant mask, is carried out to form lightly doped source/drain regions adjacent to the gate electrodes. Sidewall spacers are then formed on the gate electrodes and a second implant is used to form the heavily doped source/drain regions.
Another method by the prior art is to form the lightly doped drains (actually source/drain areas) by solid-phase diffusion from a doped oxide source that is also used as the sidewall spacers. This is best understood by referring to FIG. 1 of the prior. In this FET structure a gate oxide 14 is grown by thermal oxidation on the device area of the substrate 10, and a polysilicon,n layer is deposited and patterned to form the FET gate electrode 16. Doped sidewall spacers 20 are formed by depositing a doped oxide (e.g., phosphosilicate glass (PSG)) and anisotropically etching back to the substrate 10. After implanting the source/drain contact areas 24(N.sup.+), the substrate is annealed to drive in the dopant to form the lightly doped source/drain areas 26(N.sup.-) and to activate and anneal out the implant damage in the N.sup.+ source/drain contact areas. For an FET with a 0.2 um gate width, the effective channel length is only about 0.1 um. Unfortunately, in this process and structure, the gate electrodes 16 significantly overlay the outdiffused lightly doped source/drain regions 26(N.sup.-) resulting in high gate-to-drain capacitance that degrades the RC delay time. For example, when the gate electrode length is 0.2 um, the outdiffusion of the dopant from the sidewall spacers 20 can result in an effective FET channel length of only 0.1 um. Also, the Lightly doped source/drain areas 26(N.sup.-) extending significantly under the gate electrodes results in unwanted short channel effects, such as hot carrier injection in the gate oxide 14.
Other related references include U.S. Pat. No. 4,960,723 to Davies in which a method is taught for making self-aligned vertical FETs having an improved source contact. The source contact in the second embodiment is formed by outdiffusing from a doped oxide, but does not address the gate-to-drain overlay capacitance described above. Kurimoto et al. in U.S. Pat. No. 5,221,632 describe a method using two sidewall spacers. A first sidewall spacer composed of a material having a high dielectric constant, such as polysilicon, is used to suppress hot electron degradation by reducing the horizontal electric field around the drain. Still another approach is described by Gonzalez in U.S. Pat. No. 5,312,768 in which alternative methods of making raised source/drain areas that avoid using epitaxy and high current source/drain implants to minimize short channel effects are described. In U.S. Pat. No. 5,496,750, Moslehi teaches a method of making elevated source/drain junctions using a polysilicon layer which is implanted and subjected to an anneal to form heavily doped shallow source/drain junction regions. However, Moslehi uses conventional ion implantation to form the lightly doped drain or LDD junctions. Another approach is described in U.S. Pat. No. 5,641,698 to Lin in which polysilicon sidewalls are used to improve hot carrier immunity. However, the method uses ion implantation to form the lightly doped source/drain regions but does not use a solid-phase diffusion spacer to form the LDDs.
However, the prior-art methods described above, which use solid-phase diffusion spacers to form the LDDs, generally have high gate-to-drain capacitance. Therefore, there is still a strong need in the semiconductor industry to form FETs having shallow lightly doped drains using solid-phase diffusion spacers to provide short channel effect suppression and low gate-to-drain capacitance, while maintaining a cost-effective manufacturing process.